Multiline digital buffer



W J. WILLIS July 11, 1%?

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WILLIAM JOHN WILLIS ATTORNEYS.

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W|LLIAM JOHN WILUS W 316M110" $4 M AT TORN EYS United States Patent 3,331,060 MULTILINE DIGITAL BUFFER William John Willis, Reading, Ohio, assignor to Avco Corporation, Cincinnati, Ohio, a corporation of Delaware Original application May 7, 1962, Ser. No. 192,847, now Patent No. 3,238,298, dated Mar. 1, 1966. Divided and this application Jan. 18, 1965, Ser. No. 434,161

Claims. (Cl. 340--172.5)

ABSTRACT OF THE DISCLOSURE A time-shared serial-to-parallel data processing apparatus sequentially delivers information from a stream of groups of samples, each group representing a message fragment coming in on a separate line. Time-separated groups of the same rank represent a message. The converter operates successively on the groups. While operating on any group the converter places in temporary storage data signifying the converter status at the end of operations on the preceding group. Such data are retrieved and returned to the converter when it resumes operations on the next recurring group of the same rank as said preceding group. The operation is reversible.

The present application i a division of United States patent application Ser. No. 192,847, filed May 7, 1962, now United States Patent No. 3,238,298, issued Mar. 1, 1966.

The present invention relates to communications and data processing. More specifically, the invention provides a basically new system and method for transmitting, rout ing and handling a plurality of messages on a time-multiplex basis. The invention further provides a fundamentally novel multiline digital buffer.

Before discussing the objects of the invention, this specification will point out a few typical problems raised at message-handling and switching centers. Visualize a center having a great number of incoming information channels or message lines (originating at subscriber stations, for example) and also a large number of outgoing lines. Some of the latter may be communication lines, some may be connected to computers, others may be connected to display devices, storage devices, or additional switching or message-handling centers. The number of incoming data reception lines and outgoing data transmission lines may be on the order of 1000.

While the classic problem is to switch any one of the incoming lines into relation with any ordered one of the outgoing lines, and also to reverse the roles of some or all of the lines, that problem involves many complexities. For example, one or many of the outgoing lines may be busy when ordered, so that a desired line becomes available only on a delayed or call back basis. There may be requirements for deferred delivery of message on numerous lines. The incoming message may represent a variety of codes and frequencies. The lines are independently operated, and a large number of them may be in use or may be ordered into use at any one time. The center must be two-way or reciprocal in operation, capable of using the outgoing lines for reception and the incoming lines for transmission, and all of the operations herein discussed must be performed at extremely high speeds.

The requirement of concurrent operation of many lines has heretofore been considered by the art to require individual line equipments for storage and buffering, as well as highly complex electrical networks.

A principal object of the invention is to provide a center such that a single serial-parallel converter or equivalent is utilized successively to process the sample groups ice in sequence. That is to say, a single serial-parallel converter or equivalent processes data from a plurality of lines.

It will be observed that the converter works on" a group of samples from a given first line, then on a group of samples from another line, and so forth, finally returning to the first and repeating the sequence. Another object of the invention is to provide means whereby, when the converter interrupts work on a line and takes up another line, it stores data indicating the status of said one line and retrieves such data, to assure continuity, when processing of the first-mentioned line is resumed. The capacity of the storage device is such that, at any one time, it contains such data, as to all lines other than the one being worked on.

An object of the invention, therefore, is to provide a converter with storage so proportioned and arranged as to handle data from a large number of information channels.

A further fundamental object of the invention is to provide a system in which essentially a single converter is time-shared to convert series groups of samples to parallel information on one hand, and reciprocally, to convert parallel information into series data.

For a better understanding of the invention, together with other further objects, advantages and capabilities thereof, reference is made to the following description of the accompanying drawings in which:

FIG. 1 is, in block diagram, a schematic of a preferred form of multiline digital buffer in accordance with the invention;

FIG. 2 is a graph of a standard Teletype character, with legends used in explaining the operation of the invention as employed in communicating Teletype information;

FIG. 3 shows, in skeleton form, a suitable commutator or distributing device employed in the sampling or desampling portion of the FIG. 1 system;

FIG. 4 is a chart used in explaining the principles of differential delay exploited in the compressor used in the FIG. 1, 5 system;

FIG. 5 is a schematic, in block form, of what is described as the transmitting portion of the FIG. 1 system;

FIG. 6 is a block diagram of the logic or gating network employed in a compressor or degrouper in accordance with the invention;

FIG. 7 is a chart explanatory of the sequence of op erations of the FIG. 6 gates when performing compression by differential delay;

FIG. 8 is a schematic, in block form, of a converter in accordance with the invention;

FIGS. 9 and 10 are respectively, end view and frontal perspective views of one form of gathering revolver, or temporary storage device, suitable for incorporation in the system of FIGS. 1 and 5; and

FIG. 11 is a block diagram of an alternative form of converter for use with the invention.

In the following description, Teletype signals are chosen for purposes of illustration, but it will be understood that this illustration is not intended to constitute a limitation on the wide and general utility of the invention. Additionally, the parameters herein mentioned are intended to be illustrative and are not presented by way of limitation.

Referring now specifically to FIG. 2, there are shown the electrical levels of a standard Teletype character, such as the letter R. The input on any or all incoming lines (FIG. 1) may comprise a series of such characters when Teletype messages are being handled. The Teletype character is bivalued, with 60 milliamperes of current representing the mark condition (i.e., binary one) and zero current the space condition (i.e., binary zero). A Teletype character consists of several time divisions, called bauds or bits. A character always starts with a space, or start baud or bit-that is, an instantaneous drop to zero value followed by a binary zero condition (as shown at 18, FIG. 2). The start bit is followed by five information bauds, any one of which may be either of binary one or binary zero level and all of which are of equal duration. For R the five information bauds, in sequence, are in the code 10101. The information bits are followed by a stop band or mark. The stop bit is at the binary one level and is of longer duration than any of the information bits. Let it be assumed for purposes of this discussion that a serial Teletype input is present on each of lines 3, 2, and 1 of FIGS. 1 and 3.

In standard Teletype practice the customary rate of transmission is characters per second or 100 words per minute, six characters being deemed a word. Each character comprises 7.5 data bits or bauds (inclusive of start and stop), so that the duration of each data bit (for example, bit 16, FIG. 2) approximates 13,333 microseconds. The duration of each character is 100,000 microseconds. This rate of data transmission is so slow that a multiplicity of equipments has heretofore been required for handling of a multiplicity of lines.

The first steps in the novel method of transmission herein taught are sampling and time-division multiplexing. The input lines Nos. 1, 2, 3 are commutated into a single line 17 at a rate which is determined in the manner now described.

Let S be the number of samples required or established for complete definition or determination of each character of the signal on any line (Tou, Digital and Sampled- Data Control Systems, pp. 80 et seq, McGraw-Hill Book Company, New York, 1959). The transmission duration of each sample is extremely short in comparison to the sampling period T, which in this case is the duration of one bit such as 16 (FIG. 2). The aggregate duration of all of the samples for any bit is small compared to the duration of the bit. It will be seen, therefore, that a process of sampling the digital-coded Teletype characters renders the time-consumption required for the transmission of information capable of a large order of compression.

Let N be the number of incoming lines. Then the sampling rate is equal to S N C samples per second, where C is the number of characters per second.

By reference to FIG. 2, it will be seen that the information in the character R is, for purposes of illustration, defined by six samples, such as 18, for the start bit, six samples for each of the information bits, and nine for the stop bit. FIG. 2 is provided simply for purposes of explanation, to illustrate the principle that a digitally encoded character can be defined in terms of samples of relatively short duration, whereby the transmission time consumed by signal information is greatly compressed. In practice a larger-order constant sampling rate, such as one hundred and eighty samples per character, is used. Such practice would establish a sampling rate of 180x 256x10 per second, for 256 incoming lines. If it be assumed that there were 256 incoming lines in FIG. 3, this means that the arm 19 would rotate at 1800 revolutions per second, for a sampling rate of 460,800 samples per second.

Referring now specifically to FIG. 3, there is shown a sampling or commutating device. It comprises a rotary arm 19 connected to line 17, and a plurality of input lines designated by the legends No. 1, No. 2, No. 3, etc., up to and inclusive of line No. N, the letter N indicating the number of the last line in the plurality of input lines. Each of these input lines terminates at an individual fixed contact. A line 17 is connected to such rotary contact arm to provide a single high-speed channel. Assuming a counter-clockwise direction of rotation of arm 19, it will be understood that the sequence of samples appearing on line 17 is as follows: first a sample from line No. 1, next a sample from line No. 2, and so forth. Thus it will be seen that the first step in the invention is to sample the incoming lines sequentially to provide one sample from each, in a series. It will be understood that the arm 19 or equivalent is included within the sampling device designated by the reference numeral 20 in FIGS. 1 and 5. Since the sampling is a repetitive process, the just-mentioned series of samples is followed by another series in accordance with the same sequence, and so forth, there being 1800 series in all, per second, under the hypothetical numerical conditions assumed.

It should be noted at this point that the sampling process is no synchronized with any of the signals on the input lines, and the sampling rate is asynchronous so far as they are concerned. Further, the rigid time-positional relationship between the instant of start, designated at 12 in FIG. 2, and the first sample, such as 16, pertinent to the character, is assumed only for purposes of discussion in FIG. 2 and is not in fact present. That is to say, the taking of samples is timed by a constant-rate clock and is independent of the incoming data. Bias and distortion on the incoming line may cause more or less samples to be taken of each data bit, but a counting process discussed hereinbelow assures accurate sampling. The sampler 20, as has been indicated, samples all of the lines and puts the samples on the same high-speed data highway 17, in the form of time-division multiplex.

While the sampler illustrated in FIG. 3 is symbolically shown as a sample commutator switch, it will be understood that other well-known proper techniques in the art would in practice be used for the purpose, such as a counter and diode gating, but functionally the sampler boils down to a commutating switch and is shown as such.

The technique of repetitively successively sampling several messages greatly reduces the time of reception per message, by a substantial multiple, but this is only one of a combination of principles exploited in the present invention.

Let there now be considered he high-speed highway or channel 17, There will appear on that line a sample from No. 1, followed by a sample from line No. 2 and finally a sample from line No. N. This sequence of samples is followed by a like sequence, and 1800 of these sequences occur per second with the parameters assumed. All of these sequences taken together provide, in serial formation, the same aggregate amount of information as would be provided by ten characters on each line. Now, recalling that the assumed duration of each original character, such as the letter R, is 100,000 microseconds, so that the duration of ten characters would be one second, what is provided here, by way of illustration, is an increased rate of transmission on the order of 256i.e., N. The system is by no means limited to this particular parameter, as will be understood from the description which follows.

It will be understood that each sample in channel 17 will have either a binary one level or a binary zero level, dependent on the incoming data bit or other level of the signal being sampled.

Returning now to a consideration of FIG. 2, it will be understood that any bit or part of a character may be reconstructed by grouping together the samples representative of that bit or fragment. For example, returning now to the illustrative sequence used in FIG, 2: the first six samples, at binary zero level, can, when grouped together, signify a start bit; the next six samples can, at binary one level, signify a binary one bit; the following six samples can signify a bit at binary zero level. That is to say, any fragment of the original Teletype signal may be reconstructed in effect by grouping together a substantial number of samples, serially. This function is performed by he grouper 21 (FIGS. 1 and 5). Additionally, successive fragments of a character originating from the same incoming line are put into sequence by the converter 23. The converter 23 is time-shared and operates successively on groups of samples from the respective lines. Further, the gathering revolver 24 places in sequence the characters from each line constituting the message from that line.

The present invention is based in part on an appreciation that, by rearranging the samples appearing on line 17 in groups, the entire binary coded signal can be reconstructed, line for line. For example, if the character R be assumed to be on incoming line No. 1, the information in that character is fully set forth by a sequence of samples as follows (FIG. 2): six samples at binary zero level, six at binary one level, six at binary zero level, six at binary one level, six at binary zero level, six at binary one level, concluded by nine samples at binary one level. Armed with a group of samples from any one incoming line, the original signal may be entirely reconstructed.

The discussion pertinent to FIG. 2 postulates fortyfive samples per character; however, it has already been stated that a sampling rate of one hundred and eighty percharacter is preferred in practice.

Now then, the function performed by the grouper 21 is to place together or group, with major time compression, a substantial number of samples from line No. 1 (say twenty-seven samples), then to place together a large number of samples (say twenty-seven) from another line (say line No. 28), and to repeat this process, for any one cycle, until groups of samples from all of the lines are produced, in sequence, Now, in approaching the principle here involved, it will be assumed for purposes of discussion that the compressor 21 is working in a system in which there are only two input lines, No. l and No. 2, so that on line 17 there successively appear samples (disregarding their level for the moment) in this sequence, by lines: 2, l, 2, l, 2, l, 2, 1, 2, 1, 2, etc. This sequence is illustrated by the upper line in FIG. 4. Now in this example the number of lines N is equal to two. Now let there be delayed the first sample from line No. 2, by a time equal to three times the time interval between samplesi.e., by 3 (N1) multiplied by this time interval. Let there be delayed the second sample from line No. 2 by an amount equal to two times that intcrvali.e., by 2 (N1), to express this in abbreviated langauge leaving interval to be understood. Let the third sample from line No. 2 be delayed by one interval-Le, N. Let the fourth sample be undelayed. This process is referred to as differential delay time compression" of the samples, and the particular illustration in FIG. 4 shows how a sequence of samples from two incoming lines can be transformed into groups of four samples each. It will be observed that on the outcoming line 22 of compressor 21 there now appears a group of four samples from line No. 2, followed by a group of four samples from line No. l, the latter being followed by a group of four samples from line No. 2, and so forth. It should be noted that this represents a partial reconstruction of an original Teletype character. Moreover, an extension of this principle by the grouping together of a larger number of samples permits more of the Teletype character to be reconstructed. Assuming various fragments of the Teletype signal to be reconstructed, placing of those fragments in sequence enables entire characters to be reconstructed. The latter is the function performed by the serial-parallel converter 23.

Note that information from line No. 1 which occurred over a period of eight sample times" at the input of the compressor or grouper 21 now occurs over a period of four sample times. This is the reason why this grouping of samples is called time compression. The exact amount of delay employed for each sample is easily controlled by simple counters and logic gating, for example (FIG. 6).

Having explained the principle of differential delay time compression, I now make specific reference to FIG. 6, which illustrates one form of compressor or grouper in accordance with the invention. In explaining the simplified FIG. 4, it was observed that the first sample from line No. 2 was delayed by 3 (N1). The second sample from line No. 2 was delayed by 2 (N 1). The highest Arabic numerical prefix designated the number of samples per group minus one. Now in FIG. 6 a twentyseven sample group is desired. Therefore the FIG. 6 system comprises a clock 25, counters 26, 27, and 28, and a plurality of and and or gates so related that a 26 (N-1) delay is imposed on the first received sample from line No. l, for example, a 25 (N1) delay is imposed on the next sample from line No. 1, and so on, no delay being imposed on the twenty-seventh sample.

The FIG. 6 embodiment is a three-stage compressor having an or gate output 49 for the first stage, an or" gate output 50 for the second stage, and an or gate output 51 for the third stage. Each stage comprises two delay lines, three and gates, an or" gate, and a counter. The first stage groups the samples by threes. The second stage further groups the output of the first stage, and the output of the second stage comprises groups of nine samples. Extending the principle, the output of the third stage comprises groups of twenty-seven samples.

Considering now the first stage, it comprises the input line 17 and two delay lines 48 and 47, together with the and" gates 37, 38, and 39 and the output or gate 49. The and gate circuits (one including 48 and 47, and the other 47 only) are effectively in parallel between input line 17 and the ouput or" gate 49. The three and gates are individually coupled to counter 26, so that the counter controls the opening and closing of the gates.

Similarly, the second stage comprises the output of or gate 49, two delay lines 46 and 45, together with the and" gates 34, 35, and 36 and the output or" gate 50. The and gate circuits are effectively in parallel between gates 49 and 50, one circuit including delay lines 46 and 45, and the other circuit including 45 only. The three gates 34, 35, and 36 are individually coupled to counter 27, so that the counter controls the opening and closing of the gates.

Now as to the third stage, it comprises the output of or gate 50, two delay lines 44 and 43, together with the and gates 31, 32, and 33 and the output or gate 51. The and gate circuits of 31, 32, and 33 are effectively in parallel between the output of gate 50 and the output or gate 51, one circuit including delay lines 44 and 43, and the other circuit including 43 only. The three and" gates 31, 32, and 33 are individually coupled to counter 28, so that the counter controls the opening and closing of the last-mentioned gates.

The master clock 25 controls the counters, and it is interlocked with the counters 26, 27, and 28, the operating rate of counter 28 being one-third that of counter 27, and the operating rate of counter 27 being one-third that of counter 26. During any particular grouping of twenty-seven samples, counter 26 makes twenty-seven counts, while counter 28 makes only three, for example, and counter changes state once, at the end.

Perhaps the most simple way to understand the FIG. 6 system is to state a general law. There are imposed on the successive samples from any given source incrementally increasing delays according to the following formula: (G-g) (N 1) (time between outgoing samples), where G is the number of samples per group, g designates the reverse order of the incoming samples in any given group, and N represents the number of samples in each series. In this case the number of lines is equal to 256. Therefore (N--1) is equal to 255. G, the number of samples in each group, is 27. Therefore expression G is equal to 27. In the case under discussion, g is equal to 1, and therefore the expression (G-g) is equal to 26. 26 multiplied by 255 is equal to 6630 sample times, the delay which is to be imposed on the first sample of the group of twenty-seven samples. Before the first sample is gated into the output line 22, it is delayed by the following de lay lines, effectively in series: 47, 48, 45, 46, 43, and 44. This series arrangement of delay lines may be regarded as a series framework into which the various individual delay lines are inserted by the gates. For the processing of the first sample, all of the lines are in series to impose thereon a delay of 6630 sample times. On the other hand, for the twenty-seventh sample, none of the lines is in series, and the twenty-seventh sample passes from line 17 to line 22. This is explained in the chart of FIG. 7, the first column of which refers to the sequence of samples. The second column graphically points up the differential delay aspect, indicating the sample times of delays severally applied to the samples from the first to the twentyseventh. The next six columns designate which delay lines impose the required delay on the particular sample under discussion. The following three columns indicate the sequence of operation of the gates.

Let us consider, for example, the first, second, and third samples. The routing of the first sample is via these elements: 47, 48, 37, 49, 45, 46, 34, 50, 43, 44, 31, 51, 22. Gates 37, 34, and 31 open to pass the first sample through the three stages to or gate 51. Now as to the second sample, the routing is similar except that delay line 48 is not effective and gate 38 opens, gates 34 and 31 remaining open.

The delays of the various lines are as follows:

48(N l) or 255 sample times 47(N1) or 255 sample times 463(Nl) or 765 sample times 45-3(N l) or 765 sample times 449(N1) or 2295 sample times 439 (N l) or 2295 sample times Maximum26(N 1) or 6630 sample times Twenty-seven counts of the clock 25 after the lastmentioned sample from line No. 1 (it being undelayed) is passed through gates 39, 49, 36, 50, 33, and 51, another undelayed sample will similarly be passed directly from input line 17 to output line 22 of the compressor. The last-mentioned sample is twenty-seven beats of clock 25 behind said last sample from line No. 1, and is therefore the last sample from line No. 28. Therefore the compressor first turns out a group of twenty-seven samples from line No. 1, then a group of twenty-seven samples from line No. 28, then a group of twenty-seven samples from line 55, and so on.

Another way of looking at this is to consider that the first undelayed sample passing gate 51 from line No. 1 is the last sample from line No. l. The next sample to pass gate 51 will necessarily (see chart in FIG. 7) be a sample which is delayed 6630 sample times. It is therefore the first sample from line No. 28. Now the first 6630 samples intervening between the first sample from line No. 28 and the last sample from line No. 28 (produced by twenty-six revolutions of arm 19) are passing down the compressor delay lines at this time.

It will be understood by those skilled in the art that retiming flip-flops may be placed at the outputs of the three compressor stages. While these introduce minor additional delays into the system, the provision for such delays does not affect the principles herein involved. Additionally, the providing of retiming flip-flops wherever required is well within the skill of the art.

While in the preferred embodiment the requisite differential delay is accomplished by delay lines, which also function as storage devices, it will be understood that the essential functions of delay and storage may be performed by other means, and therefore the block 21 in FIG. 1 is intended to be construed sufiiciently broadly to include any appropriate means for performing the requisite primary functions just mentioned.

Essentially the compressor is a controlled delay line storage device with provisions for imposing on the successive samples from any given line delays according to the following formula:

where G is the number of samples per group, g designates the order of the sample in any given group (whether first, second, third, etc.), and N represents the number of incoming lines. Applying this formula to the first sample from any given line, for example, the delay is equal to (27-1) (256l), or 6630 sample times.

Now, the sequence of sample groups from the compressor 21 is applied to a single high-speed data converter 23, which is operated in a time-shared mode. Essentially what unit 23 does, in a typical cycle of operation, is to process the group of twenty-seven samples from line No. 1, then the first group from line No. 28, then the first group from line No. 55, and so on through the first groups from all lines and finally returning to the second group from line No. 1. When the information from successive groups from line No. 1 indicates the presence of a bit, the device 23 registers that bit. When the information from the successive groups from line No. 1 indicates the presence of a sufiicient number of bits to constitute a character, then the device 23 delivers that character into a gathering revolver 24, in a sector thereof dedicated to the incoming line from which the character originates. The status of the seriesparallel converter 23 at the conclusion of operations relating to a group from any particular incoming line consists of these factors: (1) a decision as to whether or not a start bit has been received on that line; (2) any data bits present; (3) the number of samples of coverage of the next data bit.

Now, it has been demonstrated that the compressor produces a sequence of groups of samples in series formi.e., a group of twenty-seven samples from line No. 1. followed by a group of twenty-seven samples from line No. 28, followed by a group of twenty-seven samples from line No. 55, and so forth. Note that the information from the lines is reconstructed in partthat is, enough for a bit, or a fraction of a character, from each line. The converter, therefore: l) converts, or conditions the first group of samples from line No. 1 for conversion, to parallel form; (2) operating in a time-shared mode, puts the status of line No. 1 information in memory and repeats the conditioning or conversion process with respect to the first group of samples from line No. 28; (3) places the status of line No. 28 information in memory; (4) similarly operates in sequence on the sample groups from all of the lines; (5) then retrieves from memory the status of the line No. 1 information and resumes operations with continuity on the second group of samples from line No. 1.

Stated in another way, the groups of samples are serially conveyed to a single high-speed data converter. This converter converts the first group of samples from line No. 1 into parallel form. Should any left-over" unconverted information remain in the converter at the time that it completes processing the first group of samples from line No. 1, this unconverted information is stored in an auxiliary memory and retrieved when the converter acts upon the second group of samples from that same line. That is to say, the converter looks at a group of samples from line No. 1 and works on those. Then it takes up a group of samples from line No. 28, and in doing so stores in auxiliary memory whatever status it had on the completion of operations on the first group from line No. 1. At the time that the converter begins to work on the second group from line No. l, the status which characterized the converter when it completed its operations on the first group from line No. 1 is restored, thus assuring continuity in the conversion of line No. 1 information into parallel form. Since the converter operates in a time-shared mode, such continuity is assured with respect to information from all of the lines.

Reference is now made to FIG. 11 for a block diagram illustrating, in principle, what this single serial-parallel converter is. It will be understood that the block 23 of FIG. 1 contains the FIG. 11 elements. The output of the compressor is applied to a serial-to-parallel converter device designated in FIG. 11 by the reference numeral 52.

The groups of samples from all of the lines flow into the single serial-parallel converter 52. The serial-parallel converter has both digital input (samples) and digital output (words or characters) and hence is purely digital itself. The converter is composed of a number of flip-flops and some logical gating. The status of the converter can be stored away and later recalled by storing away and later recalling the state of the individual flip-flops.

Each time the converter finishes processing one line and starts to process another line, it must store away the status of the former line, and retrieve the status of the latter. The status of the line includes information on how many bits of data have been received, what these bits are (ones or zeros), and how many samples of the next data bit have been counted. In addition, the status may include one or two characters which have been saved up toward making a word, an address in which the next character or word ought to be put away, and information about error checking and decryption. If this information is put away after finishing with line No. l, and is retrieved before resuming line No. l, the continuity is as if the converter were working on line No. 1 alone, even though actually the converter is working on 255 other lines.

In order to make a rapid transition from line to line, the data about the next line to be processed is retrieved serially into a shift register 53, ready for a parallel exchange of data with the converter flip-flops. Old information is put away from the shift register while new data is being taken in. Alternatively, two serial-to-parallel converters may be used.

The essential fact about the serial-parallel converter is that one converter, with delay line storage or equivalent, can handle data from many incoming lines.

The device 52 is operated on a multiplex or time-shared basis, in that it successively processes groups of data from line No. 1, line No. 28, etc. Unit 52 has an input to the shift register 53. The operation of the converter 52 and shift register 53, in conjunction, is illustrated on the supposition that the first group of samples from line No. 1 indicates the presence of a start bit and, say, three samples of a one bit. That is the status of the shift register when work on that first group has ceased. When the con verter and shift register take up work on line No. 28, information indicative of such status is placed by the shift register into an auxiliary memory or delay line 54. Now, when the converter 52 resumes operation on the line No. 1 information and initiates conversion work on the second group of samples, this work is prefaced by an operation of the shift register 53 which retrieves such status from the delay line and re-inserts it into the converter, so that the converter resumes operations on information from line No. 1 with the same status that it had when it ceased previous operations on information from line No. 1.

The FIG. 11 embodiment illustrates the principles employed in the series-parallel conversion of data in the practice of the present invention. FIG. 8 illustrates a modified form of serial-to-parallel converter, for a 128 line system. it will be understood that two FIG. 8 devices, operating alternately, comprise the content of the block 23 in FIGS. 1 and 5, for a 256 line system. One of the FIG. 8 devices processes the groups of data from lines Nos. 1 and 55, for example, and the other FIG. 8 device processes the groups of data from lines Nos. 28, 82, and so forth, the point being that, while one FIG. 8 device is operating as a data converter on a group, the other FIG. 8 device is operating as a shift register. The roles of the two devices are reversed following the processing of each twenty-seven sample group, so that the one device operates as a shift register and said other device as a converter.

The most easily understood approach to the FIG. 8 device is first to consider its operation as a shift register. The device comprises a plurality of units 55, 56, and 57. Let it be assumed that these three devices have just completed conversion processing operations with respect to a group of samples from line No. l. The next group to be processed by this device is a group from line No. 55. Be fore processing the group from line No. 55, however, the three units 55, 56, and 57 function as shift registers, in series, and store away their status in a delay line 60, to the end that such status may be retrieved at the time that conversion processing of the second group from line No. l is undertaken.

The discussion proceeds with the storing away of this statusi.e., the functioning of units 55, 56, and 57 as shift registers in series. Now, the status consists of several factors: first, the data bits in the input register 55. The input register has a capacity of seven bits, which, for example, can be the start bit and one or more of the data bits of the standard Teletype character. This register 55 is coupled by line 58 and and gate 78 to a recirculating delay line 60. During what is referred to as the line enable bar condition the register 55 shifts seven hits (indicative of the states of the bistable units in 55) through gate 78 into the delay line 60. The status further consists of three items of information provided by the data control and decision unit 56: (1) an indication as to whether or not the start of a character has been recognized; (2) an indication as to which bit of a character was being working on at the time that converting operations on a sample group ended; and (3) an indication of the level of the last bit worked on.

The latter three items of information are afforded by five bits of status information registered in unit 56. During the line enable bar condition these five bits are shifted through unit 55 and gate 78 into the delay line 60. Register 56 is coupled via line 62, an gate 63, and or gate 64 in series with register 55.

The final item included in the status, extensively discussed above, is an indication of how many samples of the last bit being worked on have been processed. This indication is furnished by six bits of data information from unit 57. During the line enable bar condition these six bits of status information are shifted from unit 57 through and gate 68, line 65, or gate 66, unit 56, line 62, and gate 63, and or gate 64 through the shift register 55 and thence into the delay line 60.

Parenthetically, the unit 57 functions as a counter during the line enable condition. Let us assume a sudden transition in the input signals from binary one level to binary zero level, as applied to unit 56. Now, the unit 57 then makes up to eleven counts, and, if on the eleventh count the level of the received signals is still at binary zero, the unit 56 will decide, or recognize, that a start bit has been received. The eleventh count is communicated by unit 57 to unit 56 via line 70, whereupon unit 56, acting via line 62 and or gate 71, resets the counter. Now, as additional samples are received, the counter resumes its count. Note that the recognition that a start bit has been received occurs approximately in the middle of the succession of samples constituting that bit. A count of twentyfour beyond that point would carry into the middle of the next bit. A count of twenty-four corresponds approximately to the number of samples between the middle of one bit and the middle of the next. However, under the conditions assumed, a start bit having been registered on the eleventh count, the counter will attain a count of only sixteen after it is reset. Note that, under this set of facts, the FIG. 8 device is processing the first information bit of a Teletype signal and has reached a point substantially short of the middle of that bit. When processing of a group of samples from line No. 1 is resumed, then the status of the counter is restored and it begins counting at sixteen, just where it left off during the previous counting, therefore assuring continuity.

From the foregoing it will be seen that the counter 57, at the end of the processing of each group, has achieved a status which it places in the delay line, via six bits of status information, along the following path: line 73, and gate 68, line 65, or gate 66, unit 56, line 62, and gate 63, or gate 64, unit 55, and line 58, as previously stated.

Returning now to the relationship between units 57 and 56, the reception of a start band was first postulated. Assuming some other baud were first received, the counter in unit 57 can achieve a count as high as twentyfour, and would provide on line 75, to unit 56, information indicative of a twenty-four count, from which the unit 56 can decide that one of the five information bauds has been received. Unit 56 receives an order from unit 57 on line 70 when a start baud is recognized, and on line 75 when an information or stop baud is recognized.

Unit 56 decides that a start bit has been received when two events occur: (1) a change of level from one to zero, then (2) a count of eleven. This of course is contingent upon a third factor, which is that unit 55 is empty and has reset units 56, 57, and 5S. Whenever the unit 57 indicates that it has reached a count of twentyfour, unit 56 will recognize that it has an information bit which should be delivered to unit 55. Therefore unit 56, when it operates as a shift register, always indicates whether it has been working on a start bit or an information bit. Unit 57 indicates on what part of the bit the work was being done.

Considering the line enable bar operating conditions, what is shown in FIG. 8 is simply a series of shift registers 55, 56, and 57. During the line enable bar condition these registers, in series, simply shift eighteen status bits into the delay line 60. The seven hits from unit 55 indicate the status of register 55 datawise with reference to the start bit, the stop bit, and any information bits coming in from line No. 1, for example. Recalling that unit 55 successively works on data from 128 lines, it will be understood that the delay line 60 always contains 127 groups of eighteen bits, one group for each of the 127 lines not being worked on.

The five bits from unit 56 are indicative of three items of information: (1) whether or not the start of a character has been recognized; (2) whether the start bit or some other bit has been worked on; and (3) the level of the bit which has been worked on.

The six bits from unit 57 indicate, in the event that an information bit or baud was being worked on (i.e., sampies which make up such a baud), whether the sample was the first, second, third, or fourth, etc., in the baud.

Clarifying the relationship between the units 57 and 56, the unit 56 makes a decision that a start bit has been received, on the basis of an abrupt decrease in input signal level from binary one to binary zero, followed by an eleven count, as indicated on line 70, during which the zero level is maintained. Once unit 56 makes a decision that a start bit has been received, it resets the counter and now looks at line 75 rather than line 70.

The terms line enable bar and line enable" have herein been referred to. The expression line enable" simply designates clock pulses applied to a plurality of gates in the system so that the units function respectively as follows: unit 56 as a data control and decision unit, unit 55 as an input register, and unit 57 as a counter. The term line enable bar designates alternate pulses which are applied to the system for the purpose of making units 55, 56, and 57 function as shift registers. During the line enable period, twenty-seven clock times long, these units process or convert serial data into parallel form, or at least partially convert said data. During the line enable bar period, again twenty-seven clock times long, only eighteen of which are required for the eighteen bits of shifted status information, the resultant work 12 product of the processing of a sample group is shifted into delay line 60.

Line neable bar pulses are applied to and" gates 77, 68, 63, and 78 for the purpose of passing shifted information into the units 57, 56, 55, and 60, respectively. It will be understood that, as bits are shifted into the delay line from the series of registers, stored information is shifted from the delay line 60 into the registers, the shifting loop being closed by line 79 between delay line 60 and and gate 77.

Line enable pulses are applied to and gates 80 and 69 in the input circuitry of units 56 and 55, respectively, to permit the flow of signal input datai.e., sample groups-and information derived therefrom into units 56 and 55, respectively.

Line enable pulses are also applied through and gate 82 to a register 83, which, when the presence of a full character is indicated, resets registers 55, 56, and 57, via lines 84, 85, and 36, respectively.

Register 55 delivers an output character in parallel on lines 87, 88, 89, 90, and 91. At the same time that unit 55 delivers a character, it of course resets the three units 5557.

During line enable, unit 57 is reset each time that unit 56 delivers a bit to unit 55.

The four lines between units 57 and 56, in addition to lines 70 and 75, are available for Teletype speeds other than the standard speed, and need not further be discussed herein.

Lines 87-91 go on the write heads (FIG. 9).

In lieu of several delay line sections per stage (FIG. 6), I can also employ, up to full capacity, a single delay line section per stage and recirculate the sampies through it according to the delay desired.

The contents of block 23 of FIG. 1 having been described in detail, and the means for delivery of received characters having been described, the discussion now proceeds to the memory or gathering revolver device 24.

The grouping of samples and conversion into characters are synchronized with the gathering revolver so that a character from a given input line is presented to the revolver only when the revolver can accept data from that line. The revolver is shown in outline form in FIGS. 9 and 10. It comprises a magnetic drum having five tracks 93, 94, 95, 96, and 97, each providing a column," as it were, for one of the five information bauds. Each track is divided into sectors such as 98, 99, and 100, one sector pertaining to each incoming line. Five write heads and five read heads, indicated by the reference numerals 101 and 102, respectively, are further provided (the read heads not being shown in FIG. 10). The revolver is one character (five bauds) wide and 6912 characters long, each sector having a capacity of twenty-seven characters.

At this stage in the specification the parameters are restated, as follows:

Transmission rate on each line words per minute, or 10 characters per second. Number of bits per char- 7.5.

acter 24. Number of samples per hit Number of samples per character 180. Sampling rate 460.8 kilocycles per second.

The control logic device 104 associated with the gathering revolver times the rotation and angular position of the drum in such a way that the drum is appropriately positioned to write characters in the proper locations in the sector respectively corresponding to the incoming lines on which the characters originate. Additionally, the control logic device 104 causes each information baud to be written by the appropriate write head.

Revolvers are well known to those skilled in the art and are described in the literature, as in Digital Computer Components and Circuits, Richards, D. Van Nostrand Co., Inc., New York, 1957, pages 296-297, and need not be described in further detail herein.

When any sector of the gathering revolver device is full, the contents may be dumped into permanent core storage, for example, a indicated by the reference numeral 106 in FIG. 1. Various types of quick-access storage methods and devices are well known to those versed in this art and need not be described further herein.

Referring again to FIG. 1, a system in accordance with the invention is operable in the reverse direction, data being withdrawn from the core storage device 106 (or from lines or some other source), fed by the revolver, which then function as a distributing revolver, to a time-shared parallel-to-series converter, which converts the parallel data into groups of samples. These groups of samples are expanded in the sample degrouper, then applied to a desampler for distribution back to the lines Nos. 1 through 256. The samples may be utilized to set bistable device in said lines to reconstruct the desired Teletype signals. In other words, the revolver, serial-to-parallel converter, sample grouper, and sampler may be reversed as to function, which is the significance of the four blocks in the lower portion of FIG. 1.

While there has been shown and described what is at present considered to be the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined in the appended claims.

Having fully described my invention, I claim:

1. A multistage differential delay network comprising three stages, an input, an output, three sets of three and gates and an or" gate having circuits connected in series to provide a direct path between said input and said output, one set for each stage, a plurality of pairs of delay line sections, two for each stage, and and gate means for inserting between the inputs and outputs of each of the stages, either two or one of said delay line sections, the time delay of each of the delay line sections associated with the third stage being three times as long as the time delay of each of the delay line sections associated with the second stage, and the time delay of each of the delay line sections of the second stage being three times as long as the time delay of each of the delay line sections associated with the first stage, and means for controlling the and gates associated with the delay line sections so as to impose on the successive samples from any given source incrementally diminished delays.

2. A time-shared serial to parallel data processor for time-sequentially delivering in message form information contained in a regularly recurring stream of group of samples, each of said groups being capable of representing only a fragment of a message, a plurality of groups of the same rank in the tream, although separated in time by groups from other ranks, being capable of representing a message, comprising, in combination:

a serial-parallel converter; a temporary storage device; means for time-multiplexing the series-parallel converter so that it operates successively on said groups;

said converter including means for storing in said temporary storage device, successively, data relating to the status of said converter during its operations on a preceding group of the same rank;

and means for retrieving from the temporary storage device into said converter, at the time that it resumes operations on the next recurring group of the same rank, the pertinent statu data from the temporary storage device.

3. A converter in accordance with claim 2 in which said temporary storage device is a delay line.

4. The combination of a cyclically operated converter time-shared by data pertinent to a plurality of channels, and means for storing data indicative of the status of the converter at the end of the conversion operation on information pertinent to any one channel and for retrieving said data in the converter on the resumption of conversion operations on information pertinent to the same line.

5. A converter in accordance with claim 4 in which the said storing and retrieving mean is a delay line.

References Cited UNITED STATES PATENTS 2,978,680 4/1961 Schulte 340-1725 3,029,414 4/1962 Schrimpf 340172.5 3,201,759 8/1965 Kelly 340172.5 3,273,131 9/1966 Strohm et al 340172.5

ROBERT C. BAILEY, Primary Examiner.

O. E. TODD, Assistant Examiner. 

1. A MULTISTAGE DIFFERENTIAL DELAY NETWORK COMPRISING THREE STAGES, AN INPUT, AN OUTPUT, THREE SETS OF THREE "AND " GATES AND AN "OR" GATE HAVING CIRCUITS CONNECTED IN SERIES TO PROVIDE A DIRECT PATH BETWEEN SAID INPUT AND SAID OUTPUT, ONE SET FOR EACH STAGE, PLURALITY OF PAIRS OF DELAY LINE SECTIONS, TWO FOR EACH STAGE, AND "AND" GATE MEANS FOR INSERTING BETWEEN THE INPUTS AND OUTPUTS OF EACH OF THE STAGES, EITHER TWO OR ONE OF SAID DELAY LINE SECTIONS, THE TIME DELAY OF EACH OF THE DELAY LINE SECTION ASSOCIATED WITH THE THIRD STAGE BEING THREE TIMES AS LONG AS THE TIME DELAY OF EACH OF THE DELAY LINE SECTIONS ASSOCIATED WITH THE SECOND STAGE, AND THE TIME DELAY OF EACH OF THE DELAY LINE SECTIONS OF THE SECOND STAGE BEING THREE TIMES AS LONG AS THE TIME DELAY OF EACH OF THE DELAY LINE SECTIONS ASSOCIATED WITH THE FIRST STAGE, AND MEANS FOR CONTROLLING THE "AND" GATES ASSOCIATED WITH THE DELAY LINE SECTIONS SO AS TO IMPOSE ON THE SUCCESSIVE SAMPLES FROM ANY GIVEN SOURCE INCREMENTALLY DIMINISHED DELAYS. 